ASIC Design Verification Engineer/RTL Design Engineer

Posted 11 Apr 2020

Mastech Digital

San Diego IT Jobs (Systems Engineer Jobs)

Duration: 12 Months Contract Location: Bay Area, CA Role: ASIC Design Verification Engineer/RTL Design Engineer in Bay area CA and Phoenix AZ Primary Skills: Infrastructure Role Description: The ASIC Design Verification Engineer, RTL Design Engineer would need to have at least 3+ year of experience. What we Offer:

  • FORTUNE Magazine’s "100 Best Companies to Work For" in the Bay area CA and Phoenix AZ.
  • Great Team and Work environment.
  • All roles are Contract-to-Hire (performance based) – long-term engagement
  • Sponsorship available.
  • OPT can apply Below are the positions open: 1 - ASIC Design Verification Engineer What Is Expected Of You:
  • Work with researchers and architects defining verification methodologies for each of the different core IP.
  • Define and track detailed test plans for the different modules and top levels.
  • Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
  • Keep track of coverage metrics and bugs encountered and fixed.
  • Implement self-testing directed and random tests.
  • Support post silicon bring up and debug activities.
  • Ability to communicate clearly. We're Looking For:
  • System Verilog OVM/UVM DV experience.
  • Knowledge of Python, Perl, shell scripting.
  • Knowledge with assertions (SVA) or others.
  • Knowledge of digital ASICs design flows.
  • Bachelor’s degree in Electrical Engineering or Computer Science or equivalent experience. Preferred Qualifications:
  • C, C++ coding, debugging experience.
  • Experience as a digital design engineer.
  • Experience with low power design.
  • FPGA implementation and debug experience.
  • Self-motivated and team player.
  • Masters in Electrical Engineering or Computer Science. 2 - RTL Design Engineer What Is Expected Of You:
  • Contribute to the development of efficient µArchitectures and contribute to ASIC digital GPU or HW Video Architecture, design and verification
  • Understand our in-house IPs needed and how they need to be integrated, connected and verified
  • Drive the top-level µArchitecture definition and develop the necessary RTL
  • Drive the chip-level integration, verification plan development and verification
  • Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
  • Support the test program development, chip validation and chip life until production maturity
  • Work with FPGA engineers to perform early prototyping
  • Support hand-off and integration of blocks into larger SOC environments
  • Assist with Algorithm analysis, verification and improvement
  • Contribute to ASIC digital architecture, design and verification
  • Ability to communicate clearly We're Looking For:
  • Experience as a Digital Design Engineer and/or a Chip Lead
  • Experience in GPU and Video Processing
  • Experience in RTL coding, synthesis and/or SoC Integration
  • Experience in digital design Architecture
  • BS Electrical Engineering/Computer Science or equivalent experience Education: Bachelor’s degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent. Experience: Minimum 3+ years Relocation: This position will not cover relocation expenses Travel: No Local Preferred: Yes
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